If the growth temperature of TMD can be lowered sufficiently to enable large-scale manufacturing, it could be a major step toward manufacturing 3D stacked CMOS with 2D semiconductors in real products for human use. Five members of Kim’s team worked at Samsung’s device research center in South Korea, so it may seem like they are on the verge of bringing the technology to market. The problem is that we need at least one more similar leap forward before we can say goodbye to silicon chips.
doping problem
At this time, we do not know how to connect TMD semiconductors to other devices. In today’s chips, connections are achieved through doping. Doping is the injection of impurities into silicon to increase its conductivity precisely at the points where it makes contact with metal traces. The implanted impurities smooth out the drop in conductivity as the signal travels between the semiconductor and highly conductive materials such as chromium, copper, and platinum.
On the atomic scale, doping replaces atoms of the host metal with foreign atoms. But how do you do that when the host material is one atom thin?
Attempts have been made to achieve some effect comparable to 2D molybdenum disulfide doping, but the process has been difficult to control. In Kim’s paper, the team writes that building high-performance chips based on 2D semiconductors requires developing TMD doping processes that can be performed at temperatures below 400 degrees Celsius. The researchers believe their technique could be useful for growing doped TMDs, but there is currently no way to do so.
Another pressing issue is cooling. Extracting heat from ultra-densely packed chips is difficult enough with a single layer of transistors. Having multiple such layers on top of each other should make the problem significantly worse. “Such devices require a heat sink area. This is what we plan to do in the future, and we will develop new cooling methods for such chips,” Kim said.
However, Kim feels that 3D stacked chips based on 2D semiconductors can dramatically improve performance from the same chip area and significantly reduce power consumption compared to standard CMOS electronics. Therefore, we argue that these challenges are worth addressing. And all of this will be needed to power future AI systems.
“We will achieve very high density AI chips,” Kim said.
Nature, 2024. DOI: 10.1038/s41586-024-08236-9
